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Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Courses and Certificate Fees
| Fees Informations | Certificate Availability | Certificate Providing Authority |
|---|---|---|
| INR 1000 | yes | IIT Guwahati (IITG) |
The fees for the course Multi Core Computer Architecture is :
| Fees components | Amount |
| Exam fees | Rs. 1,000 |
The Syllabus
Basic Computer Organization
- Review of Basic Computer Organization
- Basic operational concepts
- Fundamental of program execution
- Memory and I/O addressing
- Instruction set architecture- addressing modes, instruction set, instruction encoding and formats
- CISC vs RISC ISA
Instruction Pipeline Principles
- Performance Evaluation Methods
- Introduction to RISC Instruction Pipeline
- Instruction Pipeline and Performance
- Pipeline Hazards and Analysis
Pipeline Hazards and Branch Prediction Techniques
- Pipeline Hazards Management Techniques
- Branch Prediction
- MIPS Pipeline for Multi-Cycle Operations
Pipeline Scheduling and Speculative Execution
- Compiler Techniques to Explore Instruction Level Parallelism
- Dynamic Scheduling with Tomasulo’s Algorithm
- Speculative Execution
Superscalar Processors and GPU architectures
- Advanced Pipelining
- Multithreading and Hyperthreading
- Superscalar Processors
- GPU Architectures
Cache Memory Principles
- Introduction to Cache Memory
- Block Replacement Techniques and Write Strategy
- Design Concepts in Cache Memory
Cache Memory Optimizations
- Design issues for improving memory access time
- Basic and Advanced Optimization Techniques in Cache Memory
Cache Coherence Protocols
- Cache coherence and memory consistency
- Snoop Based and Directory Based Cache coherence Protocols
Primary Storage Systems
- Introduction to DRAM System
- DRAM organization
- DRAM Controllers and Address Mapping
Tiled Chip Multi-Core Processors & Network-on-Chip
- Tiled Chip Multicore Processors (TCMP)
- Network on Chips (NoC)
- Routing Algorithms
- NoC router – architecture
- Routing and flow control
Energy Efficient NoCs
- Introduction to deflection routing
- Energy Efficient Buffer-less NoC Routers
- Side-buffered Deflection Routers
Quality of Service for TCMPs
- QoS of NoC and Caches in TCMPs
- Emerging Trends in Network On Chips
- Domain Specific Accelerators
Instructors
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17 Jan'25, 01:56 PM
17 Jan'25, 12:39 PM
17 Jan'25, 10:23 AM
17 Jan'25, 09:50 AM
17 Jan'25, 09:29 AM
16 Jan'25, 01:46 PM
16 Jan'25, 09:55 AM
16 Jan'25, 06:29 AM
16 Jan'25, 06:11 AM
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