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Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Course Overview
The ever-increasing use of data and data storage has led to major innovations in the field of computer architecture. The gradual evolution in computer designs, networking components used or transmission of data, and devices used for storing data propose challenges to computer engineers to bring innovations in computer architecture.
The course will provide in-depth knowledge of building microprocessors, sequential processors, and pipeline processors. It will also provide insight into the working of the interior components and the microprocessors of modern times. It also focuses on teaching how to build vector processors.
The entrant will explore various types of parallelism like process level, thread-level, and vector level. They will also be learning to build interior working components including varied structures and algorithms that are required to build present-day microprocessors.
Over and above, the course is designed such that it achieves high-quality standards that are at par with Princeton University.
The Highlights
- Course instructor - David Wentzlaff
- 49 hours course
- 100% online
- Advanced level
Programme Offerings
- online
- Pre-recorded videos
Courses and Certificate Fees
| Certificate Availability |
|---|
| no |
Computer Architecture Fees Structure
| Course | Fees |
| Computer Architecture | Free |
What you will learn
After completion of the Computer Architecture Programme the participants will gain mastery over the following:
- The basics and foundation of instruction set microprocessors and microprocessors.
- The concept of pipelining and the two types of hazards involved, namely Data Hazard and structural hazard
- Controlling the hazards and technologies related to memory.
- Characteristics and classification of Cache.
- Various superscalar structures
- VLIW processors
- Learning advanced mechanisms for improving the performance of Cache.
- Protection of memory and its management
- Optimizing different vector processors
- Providing solutions to the problems using parallel programming
- Designing the interconnects for network topology and multiprocessors.
Who it is for
Admission Details
Getting admission to the course is very simple.
One can get enrolled in the following way:
Step 1: Go to the course page
Step 2: Click on ‘Enroll Now’
Step 3: Enter Details like name, email address and set login password.
Step 4: Then, you need to make the payment. Once payment is received, you can access the course.
The Syllabus
Videos
- Course Introduction
- Course Overview
- Motivation
- Course Content
- Architecture and Microarchitecture
- Machine Models
- ISA Characteristics
- Recap
Readings
- Readings
- Problem Set 1 & 1A
Videos
- Microcoded Microarchitecture
- Pipeline Basics
- Structural Hazard
- Data Hazards
Readings
- Readings
Videos
- Control Hazards, Jumps
- Control Hazards, Branch
- Control Hazards, Others
- Memory Technologies
- Motivation for Caches
Reading
- Readings
Videos
- Classifying Caches
- Cache Performance
- Superscalar 1
- Basic Two-way In-order Superscalar
- Fetch Logic and Alignment
Reading
- Readings
Videos
- Baseline Superscalar and Alignment
- Interrupts and Bypassing
- Interrupts and Exceptions
- Introduction to Out-of-Order Processors
Reading
- Readings
Videos
- Review of Out-of-Order Processors
- I2O2 Processors
- I2O1 Processors
- IO3 Processors
- IO2I Processors
Reading
- Problem Set 2
- Problem Set 1 Solutions
Videos
- Speculation and Branch
- Register Renaming Introduction
- Register Renaming with Pointers to IQ and ROB
- Register Renaming with Values in IQ and ROB
- Memory Disambiguation
Videos
- Limits of Out-of-Order Design Complexity
- Introduction to VLIW
- VLIW Compiler Optimizations
- Classic VLIW Challenges
- Introduction to Predication
Reading
- Readings
- Problem Set 3
- Problem Set 2 Solutions
Videos
- Scheduling Model Review
- Review of Predication
- Predication Implementation
- Speculation Execution
- Dynamic Events and Clustered VLIWs
- Case Study: IA-64/Itanium
Reading
- Readings
Quiz
- Midterm
Videos
- Branch Cost Motivation
- Branch Prediction Introduction
- Static Outcome Prediction
- Dynamic Outcome Prediction
- Target Address Prediction
Reading
- Readings
Videos
- Basic Cache Optimizations
- Cache Pipelining
- Write Buffers
- Multilevel Caches
- Victim Caches
- Prefetching
Reading
- Readings
Videos
- Multiporting and Banking
- Software Memory Optimizations
- Non-blocking Caches
- Critical Word First and Early Restart
Reading
- Readings
- Problem Set 3 Solutions
Videos
- Memory Management Introduction
- Base and Bound Registers
- Page Based Memory Systems
- Translation and Protection
- TLB Processing
Reading
- Readings
- Problem Set 4 & 4A
Videos
- Address Translation Review
- Cache and Memory Protection Interaction
- Vector Processor Introduction
- Vector Parallelism
- Vector Hardware Optimizations
- Vector Software and Compiler Optimizations
Reading
- Readings
Videos
- Reduction, Scatter/Gather, and the Cray
- SIMD
- GPUs
- Multithreading Motivation
- Coarse-Grain Multithreading
- Simultaneous Multithreading
Reading
- Readings
Videos
- SMT Implementation
- Introduction to Parallelism
- Sequential Consistency
- Introduction to Locks
Reading
- Readings
Videos
- Sequential Consistency Review
- Locks and Semaphores
- Atomic Operations
- Memory Fences
- Dekker's Algorithm
Videos
- Locking Review
- Bus Implementation
- Cache Coherence
- Bus-Based Multiprocessor
- Cache Coherence Protocols
Reading
- Readings
- Problem Set 4 Solutions
Videos
- More Cache Coherence Protocols
- Introduction to Interconnection Networks
- Message Passing
- Interconnect Design
Reading
- Readings
- Problem Set 5 & 5A
Videos
- Networking Review
- Topology
- Topology Parameters
- Network Performance
- Routing and Flow Control
Reading
- Readings
Videos
- Credit Based Flow Control
- Deadlock
- False Sharing
- Introduction to Directory Coherence
- Implementation
- Scalability of Directory Coherence
Reading
- Readings
- Problem Set 5 Solutions
Assignment
- Final Exam