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Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Course Overview
VLSI chip is a modern and complex chip that is often called a remarkable beast. It packs a billion transistors, logic gates employed in millions to compute and control, huge memory blocks, a third party worked, pre-designed functions that come in blocks (IP blocks or Intellectual Property blocks) embedded in the chip. How can you actually design this chip? The sequence of CAD tools that use abstract descriptions provided for the chip which are refined meticulously in steps to come up with a final design.
This course is a second part of the VLSI CAD course called the certification course on VLSI CAD Part II: Layout. The course focuses on the important tools that are used for designing and creating an ASIC (Application Specific Integrated Circuit) or an SoC design process (System of Chip). The main target of this course is to help candidates develop an understanding and better knowledge of the key geometrical and logical representations that make it feasible to map from the logic part to layout and particularly to route, place, to evaluate the perfect timing of the large logic networks.
The VLSI CAD Part II: Layout certificate programme goal is that candidates should be able to utilize and understand the working of tools right at the basic level of its fundamental logic and algorithms and the supporting data structures. The Course is well-curated to include ASIC routing and placement, technology mapping, Analysis of timing involved, etc
The Highlights
- Completely Flexible deadlines
- Self-paced course to suit schedules of working candidates.
- Approx. 24 hours of video learning material
- Certificate on completion
- Shareable certificate to LinkedIn profile and resume, etc
- Classes and course material available
- English Subtitles to class videos
- Offered by Illinois
Programme Offerings
- Self Paced Online Classes
- assignments
- video lectures
Courses and Certificate Fees
| Fees Informations | Certificate Availability | Certificate Providing Authority |
|---|---|---|
| INR 5046 | yes | Coursera |
VLSI CAD Part II Layout Fees Structure :
Course | Fee |
VLSI CAD Part II: Layout (with certificate) | Rs. 5,046 |
Eligibility Criteria
Work Experience
Candidates applying for this programme must have experience in different programming language namely, Python, C++, C, Java, etc
Candidates must also have a basic understanding of algorithms focusing majorly on the recursive algorithms. and data structures.
Candidates should understand finite state machine design, Boolean algebra, gates, Kamps, calculus and linear algebra.
Understanding of RC Linear circuits at an introductory level is a must.
Certification Qualifying Details
The Course on VLSI CAD Part II: Layout awards a certificate to all those candidates who take the complete course and also submit every graded assignment and pass them satisfactorily.
What you will learn
Candidates who complete this programme on VLSI CAD Part II: Layout will have insights on the following topics-
- Working knowledge of ASIC placement, the process, and results in synthesis. Knowledge of using mathematical optimization and an iterative method to do large scale placement tasks in VLSI
- Working with technological mapping. It is a critical step that comes between Layout and Logic. It helps candidates in translating the output of synthesis.
- Develop an understanding of VLSI CAD tools and how to utilize them in your own venture and workplace.
- Using the CAD application to create VLSI designs and hands-on experience in the field by solving assignments and problems that are given out throughout the course.
- Applying all the tools and experience of the emerging field and utilizing it to their advantage.
Who it is for
The VLSI CAD Part II: Layout programme is a relevant course that can suit candidates of multi-disciplinary range and impart an understanding of the VLSI field.
The course can be a great help to the following:
- For candidates looking to learn the VLSI CAD tools and related techniques like the Placement, layout and timing, etc to utilise in their designing careers.
- Professionals in the field of designing and CAD software use looking for answers to the complex placement and timing analysis challenges in VLSI.
- Candidates are willing to learn how CAD tools function with VLSI at the basic fundamental and algorithmic level and better utilise the experience of course in their work.
Admission Details
To take admission in this Course on VLSI CAD Part II: Layout the procedure is extremely simple. Candidates may take these simple steps to register-
Step 1: Go to the homepage of the course and press the ‘Enroll.’ button.
Step 2: Create an account with Coursera by registering with a Google / Facebook account. Existing account holders can just simply log in.
Step 3:Next the candidates can choose to buy the course by clicking enrol and then paying the course fee. Candidates can also choose to audit the course for free. However, Please note that the ‘free audit ‘option doesn’t provide a certificate.
Step 4: Candidates also have the option to choose from a free 7-day trial of Coursera plus, it is the paid version of Coursera. This is a great way to experience the premium benefits before buying.
Step 5: The candidates buying the course will have to pay the course fee from any of the available payment modes on the website.
Step 6: After the course fee payment / enrolling for the free audit course, candidates have access to the video lectures in the course and relevant reading material.
Step 7: Candidates download the videos and reading material to watch at their own pace. They can also reset deadlines in case they lose momentum due to any reason.
The Syllabus
Videos
- Welcome and Introduction
- Two Tools Tutorial
Readings
- Syllabus
- Tools For This Course
Assignment
- Demographics Survey
Plugin
- Welcome! Please tell us about yourself
Videos
- Basics
- Wirelength Estimation
- Simple Iterative Improvement Placement
- Iterative Improvement with Hill Climbing
- Simulated Annealing Placement
- Analytical Placement: Quadratic Wirelength Model
- Analytical Placement: Quadratic Placement
- Analytical Placement: Recursive Partitioning
- Analytical Placement: Recursive Partitioning Example
Readings
- Week 1 Overview
- Week 1 Assignments
Videos
- Technology Mapping Basics
- Technology Mapping as Tree Covering
- Technology Mapping—Tree-ifying the Netlist
- Technology Mapping—Recursive Matching
- Technology Mapping—Minimum Cost Covering
- Technology Mapping—Detailed Covering Example
Readings
- Week 2 Overview
- Week 2 Assignments
Assignment
- Problem Set #1
Programming Assignment
- Programming Assignment #3: Placer
Videos
- Routing Basics
- Maze Routing: 2-Point Nets in 1 Layer
- Maze Routing: Multi-Point Nets
- Maze Routing: Multi-Layer Routing
- Maze Routing: Non-Uniform Grid Costs
- Implementation Mechanics: How Expansion Works
- Implementation Mechanics: Data Structures & Constraints
- Implementation Mechanics: Depth First Search
- From Detailed Routing to Global Routing
Readings
- Week 3 Overview
- Week 3 Assignments
Assignment
- Problem Set #2
Videos
- Basics
- Logic-Level Timing: Basic Assumptions & Models
- Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks
- Logic-Level Timing: A Detailed Example and the Role of Slack
- Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths
- Interconnect Timing: Electrical Models of Wire Delay
- Interconnect Timing: The Elmore Delay Model
- Interconnect Timing: Elmore Delay Examples
Readings
- Week 4 Overview
- Week 4 Assignments
Assignment
- Problem Set #3
Programming Assignment
- Programming Assignment #4: Router
Assignments
- Problem Set #4
- Final Exam
- End of Course Survey
Plugin
- How was the course?