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Quick Facts

Total Fees
2.20 L
Exam
GATE
Seats
12

Fees Details

General

2.20 L

Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.

Course Details

MODE

Full time

DURATION

24 Months

Master of Engineering in Embedded Systems and VLSI Design is a full-time-two-year course degree offered by Osmania University, Hyderabad and approved by AICTE.


Important dates

Exams and EventsDates
GATE
Result Date (Mode - Online)
18 Mar'25 - 18 Mar'25
GATE
Score Card Date (Mode - Online)
27 Mar'25 - 30 May'25
GATE
Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'25 - 30 Dec'25
TS PGECET
Advertisement Date (Mode - Online)
11 Mar'25 - 11 Mar'25
TS PGECET
Application Date (Mode - Online)
16 Mar'25 - 18 May'25
TS PGECET
Exam Date (Mode - Offline)
15 Jun'25 - 18 Jun'25

Eligibility Criteria

Passed Bachelor’s Degree or equivalent in the relevant field. Obtained at least 50% marks (45% marks in case of candidates belonging to reserved category) in the qualifying Examination.

Admission Details

The admission into the ME course under category ‘A’ will be filled through GATE examination or a State Level Entrance Test (PGECET) conducted by the Government of Telangana State. 70% of seats covered under category ‘A’ filled by the Convener, TSPGECET, based on the rank secured in GATE/TSPGECET. 30% of the seats covered under category ‘B’ shall be filled first by sponsored candidates and vacant seats, if any, with other eligible candidates based on the merit following the guidelines issued by Government of Telangana State.

Applications for Admissions are open.

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News and Notifications
April 11, 2025 - 01:12 PM IST :

TS PGECET 2025 application forms are available from March 17, 2025 to May 19, 2025.

April 11, 2025 - 01:11 PM IST :

TS EAMCET 2025 exam will be held from April 29 to April 30, 2025.

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